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CXD2312R
9-bit 20MSPS Video A/D Converter
Description The CXD2312R is a 9-bit CMOS A/D converter for video applications. This IC is ideally suited for the A/D conversion of video signals in TVs, VCRs, camcorders, etc. Features * Resolution: 9-bit 0.5 LSB (D.L.E.) * Maximum sampling frequency: 20MSPS * Low power consumption: 130mW (at 20MSPS typ.) (Not including reference current) * TTL compatible input * Tri-state TTL compatible output (DVDD = 3.3V) * Low input capacitance * Reference impedance: 300 (typ.) 48 pin LQFP (Plastic)
Structure Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD 7 V * Reference voltage VRT, VRB VDD + 0.5 to VSS - 0.5 V * Input voltage (analog) VIN VDD + 0.5 to VSS - 0.5 V * Input voltage (digital) VIH, VIL VDD + 0.5 to VSS - 0.5 V * Output voltage (digital) VOH, VOL VDD + 0.5 to VSS - 0.5 V * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage AVDD, AVSS 5.0 0.25 DVDD, DVSS 3.0 to 5.25 | DVSS - AVSS | 0 to 100 * Reference input voltage VRB More than 1.8 VRT to AVDD - 0.4 * Analog input VIN More than 1.8Vp-p * Clock pulse width TPW1 25 (min.) TPW0 25 (min.) * Operating ambient temperature Topr -20 to + 75
V V mV V V ns ns C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94Z29C79-PS
CXD2312R
Block Diagram
AVSS 27 28 36 AVDD 18 26
VIN 39
++
-
x8 Sense Amp Coarse Correction & Latch
12 D8 11 D7 10 D6 9 D5 8 D4
VRT 29 VRT 30
DAC Coarse Comparate & Encode Fine Comparate & Encode Fine Latch Calibration Unit VRB 34 VRB 35 Sense Amp
5 D3 4 D2 3 D1 2 D0 (LSB)
21 MINV 20 LINV 19 TESTMODE
CLK 22 CE 23 OE 24
Timing Gen 41 CAL Auto Calibration Pulse Generator 17 SEL 15 RESET
Pin Configuration
36 35 34 33 32 31 30 29 28 27 26 25
AVSS
NC
VRT
AVSS
37 TSTR 38 AT 39 VIN 40 NC 41 CAL 42 TS 43 AVSS 44 AVSS 45 DVDD 46 NC 47 NC
AVDD D7
AVDD D8
VRB
VRB
NC
VRT
AVSS
NC
CE 24 OE 23 CLK 22
MINV 21 LINV 20 TESTMODE 19 AVDD 18 SEL 17 DVSS 16 RESET 15 TIN 14
DVSS
NC
DVDD
48 DVSS
TO 13
D2
D4
D1
D0
D3
1
2
3
4
5
6
7
8
-2-
D5
9 10 11 12
D6
CXD2312R
Pin Description Pin No Symbol
DVDD
Equivalent circuit
Description
2 to 5 8 to 12
D0 to D8
D0 (LSB) to D8 (MSB) output.
DVSS
13 7, 45 6, 16, 48 27, 28, 36, 43, 44
TO DVDD DVSS AVSS
AVDD
Test pin. TS = High: High impedance state Digital VDD. Digital VSS. Analog VSS.
17
SEL
17
Calibration input pulse select after completion of the startup calibration. High : Internal pulse generation Low : External input
AVSS AVDD
22
CLK
22
Clock pin.
AVSS AVDD
41
CAL
41
Calibration pulse input.
AVSS AVDD
15
RESET
15
Calibration circuit reset and startup calibration restart.
AVSS
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CXD2312R
Pin No. 14
Symbol TIN
Equivalent circuit
Description Test signal input. Normally fixed to AVDD or AVSS.
AVDD
29, 30
VRT
29 30
Reference top.
AVSS
34, 35
VRB
34 35
Reference bottom.
38
AT
Test signal output. TS = High: High impedance state Test signal input. Normally fixed to AVDD. Test signal input. Normally fixed to AVSS.
AVDD
42 37
TS TSTR
23
OE
23
D0 to D8 output enable. Low : Output state High : High impedance state
AVSS
AVDD
24
CE
24
Chip enable. Low : Active state High : Standby state
AVSS
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CXD2312R
Pin No.
Symbol
Equivalent circuit
AVDD
Description
19
TESTMODE
19
Test mode. High : Output state Low : Output fixed
AVSS AVDD
20
LINV
20
Output inversion. High : D0 to D7 are inverted and output.
AVSS
AVDD
21
MINV
21
Output inversion. High : D8 is inverted and output.
AVSS
18, 25, 26
AVDD
AVDD
Analog VDD.
39
VIN
39
Analog input.
AVSS
-5-
CXD2312R
Digital Output The following table shows the correlation between the analog input voltage and the digital output code (TESTMODE = 1, LINV, MINV = 0) Input signal voltage VRT Step 0 Digital output code MSB LSB 111111111
255 256
100000000 011111111
VRB
511
000000000
The following table shows the output state for the combination of TESTMODE, LINV, and MINV states. TESTMODE 1 1 1 1 0 0 0 0 LINV 0 1 0 1 0 1 0 1 MINV D0 D1 D2 D3 D4 D5 D6 D7 D8 0 0 1 1 0 0 1 1 P N P N 0 1 0 1 P N P N 1 0 1 0 P N P N 0 1 0 1 P N P N 1 0 1 0 P N P N 0 1 0 1 P N P N 1 0 1 0 P N P N 0 1 0 1 P N P N 1 0 1 0 P P N N 0 0 1 1
P: Forward-phase output N: Inverted output Timing Chart 1
tPW1 tPW0
Clock
1.65V
tSH Analog input HOLD N
tSL
HOLD N + 2 HOLD N + 1 tDL Data output
HOLD N + 3
N-3
N-2
N-1
N
1.65V (DVDD = 3.3V) 2.5V (DVDD = 5.0V)
Timing Chart 2
1.65V Output enable (OE)
tPEZ
tPZE 1.65V
1.65V (DVDD = 3.3V) 2.5V (DVDD = 5.0V)
Data output
Active
High Impedance
Active
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CXD2312R
Electrical Characteristics Item Max. conversion rate Min. conversion rate Analog Supply current Digital Analog Standby current Digital Reference pin current Analog input band Analog input capacitance Reference resistance value (VRT - VRB)
(Fc = 20MSPS, AVDD = 5V, DVDD = 3.3V, VRB = 2.0V, VRT = 4.0V, Ta = 25C) Symbol Fc max Fc min IADD IDDD IAST IDST IRT IRB BW CIN RREF EOT EOT = theoretical value-actual measured value EOB = actual measured valuetheoretical value AVDD - AVSS VRT - VRB AVDD = 4.75V to 5.25V VIN = 4V VIN = 2V DVDD = max VIH = DVDD VIL = 0V 4.0 3.5 1 1 20 10 25 15 0.5 0.3 1.0 0.3 13 6 2 30 20 1.0 0.5 2.3 0.8 20 -10 5 5 Conditions FIN = 1.0kHz triangular wave input FIN = 1.0kHz triangular wave input CE = High 5.0 3.0 -1dB 7.5 5.5 35 10 300 8.0 12 2.5 1.0 Min. 20 21 1.6 24 1.7 0.5 28 1.8 1.0 1.0 10.0 8.0 Typ. Max. Unit MSPS
mA A mA MHz pF
210 -30 -30
390 30
Offset voltage EOB Startup calibration start voltage Digital input voltage Analog input current Digital input current Digital output current Digital output current Tri-state output disable time Tri-state output enable time Integral non-linearity error Differential non-linearity error Differential gain error Differential phase error Output data delay Sampling delay VCAL1 VCAL2 VIH VIL AIH AIL IIH IIL IOH IOL IOZH IOZL
mV 30 V V A A mA A ns ns LSB % deg ns ns
OE = AVSS VOH = DVDD - 0.5V DVDD = min VOH = 0.4V OE = AVDD VOH = DVDD DVDD = max VOL = 0V Clock not synchronized for active high impedance Clock not synchronized for high impedance active
tPEZ tPZE
EL ED DG DP
NTSC 40 IRE mod ramp, Fc = 14.3MSPS CL = 20pF 8 0
tDL tSH tSL
18 4
-7-
CXD2312R
Item
Symbol
Conditions FIN = 100kHz FIN = 500kHz FIN = 1MHz FIN = 3MHz FIN = 7MHz FIN = 10MHz FIN = 100kHz FIN = 500kHz FIN = 1MHz FIN = 3MHz FIN = 7MHz FIN = 10MHz
Min.
Typ. 53 53 53 51 51 49 68 66 66 62 56 51
Max.
Unit
SNR
SNR
dB
SFDR
SFDR
dB
Application Circuit 1. Startup calibration + internal auto calibration
4.0V
AVDD 2.0V
4.0V 2.0V AVSS
36 35 34 33 32 31 30 29 28 27 26 25
AVSS
NC
NC
VRT
AVSS
AVDD
AVDD
VRB
VRB
NC
VRT
AVSS
37 TSTR 38 AT 39 VIN 40 NC 41 CAL 42 TS 43 AVSS 44 AVSS
CE 24 OE 23 CLK 22 AVSS Clock input
Sample & Hold AVDD
MINV 21 LINV 20 TESTMODE 19 AVDD 18 SEL 17 DVSS 16 RESET 15 TIN 14 DVSS AVSS AVDD AVDD
DVDD
AVSS
45 DVDD 46 NC 47 NC
DVSS
DVDD
48 DVSS
TO 13
NC
D1
D3
D5
D0
D2
D4
D6
D7
DVSS
1
2
3
4
5
6
7
8
9 10 11 12 is all 0.1F
Digital output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
-8-
D8
CXD2312R
Application Circuit 2. Startup calibration + external sync calibration
4.0V
AVDD 2.0V
4.0V 2.0V AVSS
36 35 34 33 32 31 30 29 28 27 26 25
AVSS
NC
NC
VRT
AVSS
AVDD
AVDD
VRB
VRB
NC
VRT
AVSS
37 TSTR 38 AT 39 VIN 40 NC
CE 24 OE 23 CLK 22 AVSS Clock input
Sample & Hold
MINV 21 LINV 20 TESTMODE 19 AVDD 18 SEL 17 DVSS 16 RESET 15 TIN 14 DVSS AVSS AVDD AVDD
Calibration pulse AVDD
41 CAL 42 TS 43 AVSS 44 AVSS
DVDD
AVSS
45 DVDD 46 NC 47 NC
DVSS
DVDD
48 DVSS
TO 13
NC
D4
D6
D1
D3
D5
D0
DVSS
D2
1
2
3
4
5
6
7
8
9 10 11 12 is all 0.1F
Digital output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
-9-
D7
D8
CXD2312R
Application Circuit 3. Only startup calibration (Less than supply voltage fluctuation range of AVDD = 100mV and reference voltage fluctuation range of |VRT - VRB| = 200mV)
4.0V
AVDD 2.0V
4.0V 2.0V AVSS
36 35 34 33 32 31 30 29 28 27 26 25
AVSS
NC
NC
VRT
AVSS
AVDD
AVDD
VRB
VRB
NC
VRT
AVSS
37 TSTR 38 AT 39 VIN 40 NC 41 CAL 42 TS 43 AVSS 44 AVSS
CE 24 OE 23 CLK 22 AVSS Clock input
Sample & Hold AVDD
MINV 21 LINV 20 TESTMODE 19 AVDD 18 SEL 17 DVSS 16 RESET 15 TIN 14 DVSS AVSS AVDD AVDD
DVDD
AVSS
45 DVDD 46 NC 47 NC
DVDD
NC
DVSS
48 DVSS
TO 13
D4
D6
D1
D3
D5
D0
DVSS
D2
1
2
3
4
5
6
7
8
9 10 11 12 is all 0.1F
Digital output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 10 -
D7
D8
CXD2312R
1. Calibration Function In order to achieve superior linearity, the CXD2312R has a built-in calibration circuit and a calibration pulse auto generation circuit which is used to execute a calibration circuit. Fig. 1 shows a block diagram of the calibration pulse generation circuit.
AVDD 1 16 14 bit Counter CLR AVDD AVSS VRT VRB RESET CE
DQ
OUT
CLK
CO
CLR
Sence Amp 1 Sence Amp 2
24 bit Counter CLR
CO
SEL CAL
Fig. 1. Calibration Pulse Generation Circuit (1) Startup Calibration Function Over 600 calibration pulses are needed to complete the initial calibration process when the power is first supplied to the IC. The startup calibration function automatically generates these pulses internally and completes the initial calibration process. The following five conditions must be satisfied to initiate the startup calibration function.
When RESET = High and CE = Low [V] 5 AVDD VRT
2.5 1V 0 Sence Amp 1 Sence Amp 2 CLR
VRB
[t]
a) The voltage between AVDD and AVSS is approximately 2.5V or more. b) The voltage between VRT and VRB is approximately 1V or more. c) The RESET pin (Pin 15) must is high. d) The CE pin (Pin 24) must is low. e) Condition b is met after condition a. Once all five of these conditions have been met, the calibration pulses are generated. The pulses are generated by counting 16 main clock cycles on a 14-bit counter and closing the gate when the carry-out occurs. Therefore, the time required for startup calibration after the above five conditions have been met is determined by the following formula:
Startup calibration time = main clock cycle x 16 x 16,384 For example, if the main clock frequency is 14.3MHz, the time required for startup calibration is 18ms.
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CXD2312R
(2) Auto Calibration Pulse Generation Function After startup calibration is completed, this function periodically generates calibration pulses so that calibration can be performed constantly without any need for input of calibration pulses from an external source. This function counts 16 main clock cycles on a 24-bit counter and uses the carry-out as the calibration pulse. The cycle of the calibration pulse generated in this fashion is as follows: Internal calibration pulse generation cycle = main clock cycle x 16 x 16,777,216 Therefore, if the main clock frequency is 14.3MHz, the calibration pulse cycle is approximately 19 seconds; since calibration is performed once every seven pulses, the calibration cycle is approximately 130 seconds. In order to use this function, the SEL pin (Pin 17) must be high. Note that this function cannot be used if fixing the lower bits in the calibration operation as described below will cause problems because this function is executed asynchronously without regard to the input signals. (3) External Calibration Pulse Input Function If the auto calibration function cannot be used, calibration can be performed in synchronization with the input signals when a calibration pulse is input from the CAL pin (Pin 41) by setting the SEL pin (Pin 17) low.
10ns or more 7clock CLK 1clock or more
CAL
D4 to D8
N-3 N-2
N-1
N
N+1
N+2 N+3
N+4
N+5
D0 to D3
N-3 N-2
N-1
N
N+5
Fig. 2. Calibration Timing Chart Calibration starts when the falling edge of the pulse input to the CAL pin (Pin 41) is detected. Because the lower comparator is occupied for four clock cycles at this point, the previous lower data is held for four clock cycles after seven clock cycles since the rising edge of the clock cycle in which the falling edge of CAL was detected. Calibration can be performed outside of video intervals by using the sync signal, etc., to input the CAL signal. An example of this is shown below. (1) Inputting CAL every H-sync
Input CLK CAL
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CXD2312R
(2) Inputting CAL every V-sync
Input CLK RESET CAL
It is also possible to use only the startup calibration function by leaving the SEL pin (Pin 17) low and fixing the CAL pin (Pin 41) either high or low. Note that this method requires restriction of the fluctuation range of the supply voltage and the reference voltage. (4) Re-initiating the Startup Calibration Function The startup calibration function can be re-initiated after the power and reference voltage are supplied by using the CE pin (Pin 24) and the RESET pin (Pin 15). Particularly in cases where the riseup characteristics of the power supply and the reference voltage are unstable, it is possible to initiate startup calibration properly by connecting a CR and delaying startup until after power supply riseup.
AVDD R RESET 15 C AVSS
[V]
AVDD VRT RESET
VRB
[t]
Fig. 3. Initiation of the Startup Calibration Function Using the RESET pin
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CXD2312R
2. Power supply To prevent the influence of noise, connect the power supply to a 0.1F by-pass capacitor as near the device as possible. 3. DVDD Either a 3.3V or 5.0V digital power supply can be used. Compared to the 5.0V power supply, the 3.3V power supply generates a decreased amount of radiation noise but offers a decreased drive capacity. These two power supplies do not virtually differ in static and dynamic characteristics. Further, the High output level rises up to DVDD. 4. Reference input The voltage to be supplied to the reference pins must be driven by a buffer having a 10mA or more drive capacity. For supplied voltage stabilization, connect the buffer to a 0.1F by-pass capacitor as near the pins as possible. 5. Latch-up Ensure that the AVDD and DVDD pins share the same power supply on a board to prevent latch-up which may be caused by power ON time-lag. 6. Board To obtain full-expected performance from this IC, be sure that the mounting board has a large ground pattern for lower impedance. It is recommended that the IC be mounted on a board without using a socket to evaluate its characteristics adequately.
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CXD2312R
Example of Representative Characteristics
Supply current vs. Ambient temperature
Fc = 20MHz fin = 1kHz triangular wave AVDD = 5.0V DVDD = 3.3V
Maximum operating frequency [MHz]
Maximum operating frequency vs. Ambient temperature
35 fin = 1kHz triangular wave AVDD = 5.0V DVDD = 3.3V
Supply current [mA]
25
30
23
25
21
20 -20 0 25 50 75
-20
0
25
50
75
Ambient temperature [C]
Ambient temperature [C]
Output data delay vs Ambient temperature
Sampling delay vs. Ambient temperature
Output data delay [ns]
17
Sampling delay [ns]
TSH 6 AVDD = 5.0V DVDD = 3.3V Fc = 1MHz TSL 2
15
13
AVDD = 5.0V DVDD = 3.3V Fc = 1MHz CL = 20pF
4
-20 0 25 50 Ambient temperature [C]
75
-20
0 25 50 Ambient temperature [C]
75
Input frequency vs. SNR
AVDD = 5.0V DVDD = 3.3V Fc = 20MHz VIN = 2Vp-p Ta = 25C
Input frequency vs. SFDR
60
60
SFDR [dB]
SNR [dB]
50
50
40
40
AVDD = 5.0V DVDD = 3.3V Fc = 20MHz VIN = 2Vp-p Ta = 25C
100k
1M 10M Input frequency [Hz]
100k
1M 10M Input frequency [Hz]
Input frequency vs. Effective bits
Input band
Effective bits [bit]
Output level [dB]
9 AVDD = 5.0V DVDD = 3.3V Fc = 20MHz VIN = 2Vp-p Ta = 25C
1 0 -1 -2 -3 AVDD = 5.0V DVDD = 3.3V Fc = 20MHz VIN = 2Vp-p Ta = 25C
8
7
100k
1M
10M
100k
1M
10M
Input frequency [Hz]
Input frequency [Hz]
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CXD2312R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24
(8.0)
EPOXY RESIN 0.2g
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
(0.22)
+ 0.05 0.127 - 0.02 0.13 M 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SOLDER/PALLADIUM PLATING 42/COPPER ALLOY
- 16 -
0.5 0.2

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